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Semiconductor Analysis
Semiconductor TEM Metrology
Metrology with transmission electron microscopy for fast, automated, and highly precise measurements, accelerating time-to-data and maximizing yields.
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Semiconductor devices are becoming more complex due to the demand for faster speeds, shorter time-to-yield, and time-to-market. Scanning transmission electron microscopy (S)TEM metrology has become a necessary element of all leading-edge wafer fabrication workflows, since highly specific measurements are needed to generate statistically relevant data with sub-angstrom accuracy. This data allows manufacturers to calibrate toolsets, diagnose failure mechanisms, and optimize overall process yield.
Thermo Fisher Scientific offers metrology workflows that are flexible enough to enable manual, semi-automated, or even fully automated solutions, depending on your needs. The Thermo Scientific Metrios AX System is the first TEM designed to provide the fast, precise measurements that semiconductor manufacturers need to develop and control their wafer fabrication processes. Learn more by visiting the Metrios product page below.
TEM metrology workflow example
Example of the STEM metrology dimensions used to assess the line roughness (LER/LWR) on a 300 mm post-lithography (EUV exposure) and post-etch wafer. This mimics part of a multiple step patterning process used to produce gate fins for the 10 nm technology node.
Example of the STEM metrology dimensions used to assess the line roughness (LER/LWR) on a 300 mm post-lithography (EUV exposure) and post-etch wafer. This mimics part of a multiple step patterning process used to produce gate fins for the 10 nm technology node.
Metrology extracted from energy-dispersive X-ray spectroscopy (EDS) elemental maps of a planar-cut 3D NAND memory bit, measuring the circular dimensions of poly-Si channel, blocking oxide, tunnel oxide, and Si3N4 trap layers.
An example of automated metrology measurements taken for a 14-nm fin-cut sample, to measure the gate oxide dimensions as well as the fin height relative to two important process etch steps.
Example of the STEM metrology dimensions used to assess the line roughness (LER/LWR) on a 300 mm post-lithography (EUV exposure) and post-etch wafer. This mimics part of a multiple step patterning process used to produce gate fins for the 10 nm technology node.
Metrology extracted from energy-dispersive X-ray spectroscopy (EDS) elemental maps of a planar-cut 3D NAND memory bit, measuring the circular dimensions of poly-Si channel, blocking oxide, tunnel oxide, and Si3N4 trap layers.
An example of automated metrology measurements taken for a 14-nm fin-cut sample, to measure the gate oxide dimensions as well as the fin height relative to two important process etch steps.